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上电时,什么时候让6678的时钟输入有效?

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SPRS691E—March 2014文档中,p122中,有如下说明:Once CVDD is valid it is acceptable that the P and N legs of these CLKs may be held in a static state (either
high and low or low and high) until a valid clock frequency is needed at that input.

请问:我怎么知道6678什么时候需要输入时钟?


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